A collection of common Xilinx Vivado attributes.
val async_reg : bool -> tInform Vivado that a registers data input is asychronous to it's clock.
val dont_touch : bool -> tInstruct the synthesizer and place & route tools to keep the node. Cannot be applied to a port.
val keep_hierarchy : bool -> tSetting keep_hierarchy to yes will prevent Vivado from optimizating across module boundaries. Can only be applied to modules or instances.
val fsm_encoding :
[ `auto | `gray | `johnson | `none | `one_hot | `sequential ] ->
tSelect encoding of finite state machine. Apply to state register.
val mark_debug : bool -> tExport net for debugging with chipscope.
val keep : bool -> tSimilar to dont_touch
module Ram_style : sig ... endmodule Srl_style : sig ... endSRL_STYLE instructs the synthesis tool on how to infer SRLs that are found in the design. Accepted values are