package hardcaml

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package hardcaml
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Hardware generation in an imperative style.

This module is undergoing significant rewriting and refactoring, and subject to many breaking changes.

type var
type 'a t
include Base.Monad.S with type 'a t := 'a t
val (>>=) : 'a t -> ('a -> 'b t) -> 'b t
val (>>|) : 'a t -> ('a -> 'b) -> 'b t
module Monad_infix : sig ... end
val bind : 'a t -> f:('a -> 'b t) -> 'b t
val return : 'a -> 'a t
val map : 'a t -> f:('a -> 'b) -> 'b t
val join : 'a t t -> 'a t
val ignore_m : 'a t -> unit t
val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t
module Let_syntax : sig ... end
val skip : Base.unit t

skip 1 cycle

val wait : Base.int -> Base.unit t

skip n cycles

val par : ?comb_fin:Base.bool -> 'a t Base.list -> 'a Base.list t

Perform ts in parallel. comb_fin controls the finish signal generation. When false and extra cycle is taken after the ts complete to generate the fin signal. Otherwise extra combinatorial logic is generated to ensure the fin signal toggles on the same cycle as the last t to complete.

val par2 : ?comb_fin:Base.bool -> 'a t -> 'b t -> ('a * 'b) t
val (|||) : 'a t -> 'b t -> ('a * 'b) t
val cond : Signal.t -> 'a t -> 'b t -> Base.unit t

cond c t f performs t if c is high, otherwise performs f

val iter : Signal.t -> 'a t -> 'a t

iter c t perform t while c is high

val forever : 'a t -> 'a t

perform t forever

val wait_while : Signal.t -> Base.unit t

wait until t is low

val wait_until : Signal.t -> Base.unit t

wait until t is high

val follow : clock:Signal.t -> enable:Signal.t -> Signal.t -> 'a t -> Signal.t * 'a

follow t and get result

val new_var : ?name:Base.string -> Base.int -> var t

create an new n bit register

val read_var : var -> Signal.t t

read value of register

val assign : (var * Signal.t) Base.list -> Base.unit t

assign list of registers - takes 1 cycle

val write_var : var -> Signal.t -> Base.unit t

write register with value

val modify_var : (Signal.t -> Signal.t) -> var -> Base.unit t

modify current value of resgiter

val rewrite_var : (Signal.t -> Signal.t) -> var -> var -> Base.unit t

read a register, modify value, write a second register

module type Same = sig ... end
module Same (X : Interface.Pre) : Same with type 'a same = 'a X.t
module SVar : Same with type 'a same = 'a
module SList : Same with type 'a same = 'a Base.list
module SArray : Same with type 'a same = 'a Base.array
module STuple2 : Same with type 'a same = 'a * 'a
module STuple3 : Same with type 'a same = 'a * 'a * 'a
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