package hardcaml
Install
Dune Dependency
Authors
Maintainers
Sources
sha256=0dc4153de7ffa0a3471d9ecd8044f701e300290ce4c2e716187e063e8cf2f8b1
Description
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Published: 21 Mar 2022
README
"Hardcaml"
Hardcaml is an OCaml library for designing and testing hardware designs.
Express hardware designs in OCaml
Make generic designs using higher order functions, lists, maps, functors...
Simulate designs in OCaml
Convert to (hierarchical) Verilog or VHDL
Write new modules to transform or analyse circuits, or provide new backends
Install
$ opam install hardcaml ppx_deriving_hardcaml hardcaml_waveterm
Documentation
Related tools and libraries
Simulation and testing
Hardcaml_waveterm
- ASCII based digital waveforms. Usable in expect tests or from an interactive terminal application.Hardcaml_c
- convert Hardcaml designs to C-based simulation models. Provides an API compatible with the standard Cyclesim module. Trades compilation time for runtime performance.Hardcaml_verilator
- Convert Hardcaml designs to very high speed simulation model using the open source Verilator compiler.Hardcaml_step_testbench
- Monadic testbench API. Control multiple tasks synchronized to a clock without converting to a statemachine coding style.
Design libraries
Hardcaml_circuits
- A library of useful/interesting Hardcaml designsHardcaml_fixed_point
- Fixed point arithmetic with rounding and overflow controlHardcaml_xilinx
- Various Xilinx primitives wrapped with Hardcaml interfaces and simulation modelsHardcaml_xilinx_components
- Tool to read Xilinx unisim and xpm component definitions and generate Hardcaml interfaces
Other ...
Hardcaml_of_verilog
- Convert a verilog design to Hardcaml using YosysHardcaml_verify
- SAT based formal verification tools for Hardcamlhardcaml_mips
- A simple 5-stage MIPs CPU with associated blog detailing the development process.hardcaml_arty
- Infrastructure targetting the Arty A7 board.
Dependencies (10)
-
zarith
>= "1.11"
-
ppxlib
>= "0.23.0"
-
dune
>= "2.0.0"
-
topological_sort
>= "v0.15" & < "v0.16"
-
stdio
>= "v0.15" & < "v0.16"
-
ppx_sexp_conv
>= "v0.15" & < "v0.16"
-
ppx_jane
>= "v0.15" & < "v0.16"
-
bin_prot
>= "v0.15" & < "v0.16"
-
base
>= "v0.15" & < "v0.16"
-
ocaml
>= "4.11.0"
Dev Dependencies
None
Used by (12)
- hardcaml-lua
-
hardcaml_c
< "v0.16.0"
-
hardcaml_circuits
< "v0.16.0"
-
hardcaml_fixed_point
< "v0.16.0"
-
hardcaml_of_verilog
< "v0.16.0"
-
hardcaml_step_testbench
< "v0.16.0"
-
hardcaml_verify
< "v0.16.0"
-
hardcaml_verilator
< "v0.16.0"
-
hardcaml_waveterm
= "v0.15.0"
-
hardcaml_xilinx
< "v0.16.0"
-
hardcaml_xilinx_components
< "v0.16.0"
-
ppx_deriving_hardcaml
= "v0.15.0"
Conflicts
None