package hardcaml

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package hardcaml
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VHDL and Verilog netlist generation

module Language : sig ... end
module Output_mode : sig ... end

RTL generation options.

module Blackbox : sig ... end

Control blackbox generation. None implies blackboxes are not used. Top means the circuit will be turned into a blackbox. Instantiations means that the top level circuit will be written as normal, but submodules will be written as blackboxes.

module Uid_with_index : sig ... end
type signals_name_map_t = Base.string Base.Map.M(Uid_with_index).t
val output : ?output_mode:Output_mode.t -> ?database:Circuit_database.t -> ?blackbox:Blackbox.t -> Language.t -> Circuit.t -> Base.unit

Write circuit to Verilog or Vhdl. Instantiations are (recursively) looked up in database and if a circuit exists it is also written. The output_mode specifies how the circuit should be written - either to a single file (or buffer, or channel) or to a directory with one file for each for the top level circuit and any instantiated circuits contained in the database.

val print : ?database:Circuit_database.t -> ?blackbox:Blackbox.t -> Language.t -> Circuit.t -> Base.unit

print is output ~output_mode:(To_channel stdout)

module Digest : sig ... end
module Expert : sig ... end
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