package hardcaml_of_verilog

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type t =
  1. | Proc
  2. | Flatten
  3. | Memory of {
    1. nomap : Base.bool;
    }
  4. | Opt of {
    1. mux_undef : Base.bool;
    }
  5. | Clean
val sexp_of_t : t -> Sexplib0.Sexp.t
include Ppx_compare_lib.Equal.S with type t := t
val equal : t -> t -> bool
val to_string : t -> Base.string
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